The present invention relates to digital data processing and, more particularly, to apparatus which programmably adjusts the handling and prioritization of multiple device interrupts. The invention has application, for example, as a highly flexible means for coordinating interrupts by low-level devices vying for CPU (Central Processing Unit) time.
Conflicts relating to requests for computer processing time are unavoidable. Even with the great improvements over the past few years in clock speeds and data transfer rates, a computer cannot operate infinitely fast. As such, requests to the CPU, or "interrupt" requests, tend to accumulate. Simultaneous interrupts exemplify the problem, since it is clear that choices must be made between the several requests. The computer should choose, for example, to prevent a system crash before it prints a document. Thus, pending interrupts should generally be prioritized so that the most urgent interrupt request is answered first.
Assigning priorities to device interrupts properly considers the origination of the generated request. Interrupt conflicts can occur at several levels. Most users are familiar with the high-level conflicts associated with the several peripheral devices, such as a printer or secondary disk drive. A plurality of connected peripheral devices queuing for CPU time is typical for the modern computer system. But the occurrences of these device interrupts are relatively infrequent. Printer interrupts, for instance, usually occur after a user prompts the system.
Low-level requests to the CPU, on the other hand, occur almost invisibly to the operator. They are also dynamic and frequent. Timers, scanners, and Direct Memory Access (DMA) engines are examples of internally connected devices which generate interrupt requests to the CPU. The functioning of these devices is much more intimate with the CPU; even their physical locations are much closer.
Therefore, the approach and benefits in assigning priority levels to multiple device interrupts depends to some extent upon the level at which the conflicting devices occur. Adjusting the priority of peripheral device interrupts, for instance, would entail design methodology quite different from the low-level, dynamic device interrupts of DMA engines and timers. It may be sufficient, for example, to hardwire peripheral devices according to their desired relative priority.
In practice, some methods exist to prioritize device interrupts, but they are typically geared towards the high-level request conflicts of the external or peripheral devices, not low-level interrupt conflicts. The schemes commonly involve fixed-level priorities, whereby either the device or data channel is labeled, or rely upon temporal criterion, like the time of occurrence. Moreover, the assignation of relative interrupt priorities is usually cumbersome and restricted to serial, single-level priorities.
For example, U.S. Pat. No. 3,925,766, entitled "Dynamically Variable Priority Access System", describes how interrupt priority assignments can be made for access to data Processing memory. An information exchange control unit is hooked to the CPU and contains a series of flip-flops which gate a priority network for the appropriate peripheral interrupt. The approach re-routes the interrupt signal into a fixed set of transmission lines representing the priority selection matrix. It does not allow for equal or secondary priorities.
Similarly, U.S. Pat. No. 4,644,467, entitled "Multi-Level Dynamic Priority Selector Groups of Data Elements", describes daisy chain interface circuitry specific to an external interrupt generating device which is programmably assigned priority codes through the issuance of predetermined address codes. A code monitor then locates the element with the highest priority. The teaching again does not describe equal or secondary priorities.
These and other teachings are difficult to apply to, or are too inflexible for, low-level device priority manipulation. Nevertheless, a user or system designer would find it extremely beneficial to adjust the priority of the low-level interrupts depending upon the desired process task at hand. For example, a DMA engine is logic, internal to an input/output processor (IOP), that moves large blocks of data directly between system memory and a connected device. Under certain circumstances, this may become a critical function to the user. Hence, that user would Prefer a high priority for the DMA engine at that time. Because the interrupt occurrences are highly frequent, significant amounts of processing time could be allocated to the DMA engine in favor of, for example, the IOP timer. Programmably adjusting the priority of the DMA engine would be beneficial.
To this end, the prioritization schemes developed in the art are inappropriate. Thus, there remains a need for an interrupt priority controller that enables relatively easy interrupt priority alteration of connected low-level devices.
Accordingly, it is an object of the present invention to provide an improved interrupt priority encoder.
It is further the object of this invention to provide an interrupt priority controller which provides for primary and secondary priority designation of connected devices.
Yet another object of this invention is to provide a priority interrupt encoder that allows system users to fine-tune system performance according to desired tasks.
Other objects of the invention are evident in the description that follows.